Semiconductor devices are typically classified as either volatile semiconductor devices, which require power to maintain storage of data, or non-volatile semiconductor devices, which can retain data even upon removal of a power source. An example non-volatile semiconductor device is a flash memory device, which generally includes a matrix of memory cells arranged in rows and columns. Each memory cell in the matrix includes a transistor structure having a gate, a drain, a source, and a channel defined between the drain and the source. Each memory cell is located at an intersection between a word line and a bit line, wherein the gate is connected to the word line, the drain is connected to the bit line, and the source is connected to a source line, which in turn is connected to common ground. The gate of a conventional flash memory cell generally comprises a dual-gate structure, including a control gate and a floating gate, wherein the floating gate is suspended between two oxide layers to trap electrons that program the cell.
Flash memory devices may in turn be classified as NOR or NAND flash memory devices. Of these, NAND flash memory typically offers faster program and erase speeds, in large part due to its serialized structure, whereby program and erase operations may be performed on entire strings of memory cells.
However, given that the usage of NAND flash memory has increased significantly, there are some markets in which high performance read operations and data retention are becoming more important than program performance. For instance, high read cycles and good data retention are required for game cards, and automotive GPS systems, among other markets. Thus, there is a growing need for NAND flash memory devices that demonstrate greater data retention and read performance while maintaining the faster program and erase speeds.
NAND flash memory devices program memory cells using Fowler-Nordheim tunneling, which can pull electrons from a substrate into a floating gate and fill its traps due to high voltage (or potential) drop between a word line and the substrate. When electrons fill these traps, the potential barrier between the oxide layers and the floating gate increases. While future program operations will continue to apply the same charge to the memory cell as past program operations, the increased potential barrier of the oxide layers reduces the charge added to the floating gate during a program operation, and thus results in a high threshold voltage of the memory devices.
Some attempts to improve performance have focused on avoiding disturbances to memory cells. Specifically, flash memory devices are susceptible to memory corruption over time as a result of repeated program and read operations, which can cause “disturbs” to memory cells that are not the subject of the program or read operations. For instance, when performing a program operation of a memory cell in a selected word line, a program voltage (Vpgm) is applied to the selected word line while a pass voltage (Vpass) is applied to the unselected word lines. The pass voltage applied to the unselected word lines must be sufficiently high that the boost will be also high enough to last for the entire program operation, while too high a value increases the probability that cells sharing the same string of the selected cell will suffer a program operation.
Thus, to avoid disturbs, some efforts have attempted to adjust the operating conditions of the nonvolatile memory device by reducing the pass voltage to a level less likely to cause read disturbs. However, decreasing the pass voltage requires a decrease in the program verify (PV) voltage threshold to retain a similar pass voltage window (the range of pass voltages that largely avoid read disturbs and program disturbs). Reducing the pass voltage hinders the memory window of the nonvolatile memory device.
Accordingly, there is a need in the art to increase the performance of program operations of a non-volatile memory device.